Harris Semiconductor cd74hc166 free download

File name cd74hc166.pdf

Data sheet acquired from Harris Semiconductor SCHS157 CD74HC166, CD74HCT166 High Speed CMOS Logic 8-Bit Parallel-In/Serial-Out Shift Register at VCC = 5V · HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il 1µA at VOL, VOH February 1998 Features · Buffered Inputs · Typical fMAX = 50MHz at VCC = 5V, CL = 15pF, TA = 25oC · Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads · Wide Operating Temperature Range . . . -55oC to 125oC · Balanced Propagation Delay and Transition Times · Significant Power Reduction Compared to LSTTL Logic ICs · HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC [ /Title (CD74 HC166 , CD74 HCT16 6) /Subject (High Speed CMOS Logic 8-Bit ParallelIn/Seri Ordering Information PART NUMBER CD74HC166E CD74HCT166E CD74HC166M CD74HCT166M CD54HC166W NOTES: 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Wafer and die is available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information. TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 16 Ld PDIP 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC Wafer PKG. NO. E16.3 E16.3 M16.15 M16.15 Pinout CD74HC166, CD74HCT166 (PDIP, SOIC) TOP VIEW DS 1 D0 2 D1 3 D2 4 D3 5 CE 6 CP 7 GND 8 16 VCC 15 PE 14 D7 13 Q7 12 D6 11 D5 10 D4 9 MR CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © Harris Corporation 1998 File Number 1501.1 1 CD74HC166, CD74HCT166 Functional Diagram D0 D1 D2 D3 D4 D5 D6 D7 PE PARALLEL ENABLE CIRCUIT D0 DS 8 - REGISTERS Q7 CP CE MR D7 TRUTH TABLE INPUTS PARALLEL MASTER RESET L H H H H H PARALLEL ENABLE X X L H H X CLOCK ENABLE X L L L L H CLOCK X L SERIAL X X X H L X D0 D7 X X a...h X X X Q0 L Q00 a H L Q00 INTERNAL Q STATES Q1 L Q10 b Q0n Q0n Q10 OUTPUT Q7 L Q0 h Q6n Q6n Q70 NOTES: H = High Voltage Level L = Low Voltage Level X = Don't Care = Transition from Low to High Level a...h = The level of steady-state input at inputs D0 thru D7, respectively. Q00, Q10, Q70 = The level of Q0, Q1, or Q7, respectively, before the indicated steady-state input conditions were established. Q0n, Q6n = The level of Q0 or Q6, respectively, before the most recent transition of the clock. 2 CD74HC166, CD74HCT166 Absolute Maximum Ratings DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . .